Semiconductor type: GaN, Si, GaAs
Device type: HEMT, HBT, LDMOS
Circuit type: Doherty, Class AB
Psat – PAR; where Psat is defined as 3dB compression point of power level over the entire operating bandwidth, and PAR is peak-to-average ratio
Absolute power level can range from 0.25W (24dBm) to 100W (50dBm)
-20 -> -35 dBc
-50 -> -65dBc*; *performance depends on 1) PA topologies and devices, 2) bandwidth of PA, 3) operating power level in relation to Psat – PAR, 4) instantaneous bandwidth in relation to compensation bandwidth, 5) target processing resources, 6) baseline transceiver performance
- FPGA to apply waveforms, apply CFR/ DPD
- CMOS integrated transceiver, RF DAC, or discrete transceiver
- Low noise amplifier with sufficient gain to drive PA
- Signal analyzer
NanoSemi’s linearizer is currently using Xilinx FPGAs such as ZC706-2, ZC706-3, and Virtex 7 evaluation boards because the FMC connectors of FPGA and CMOS transceiver evaluation boards are pin-compatible.
However, NanoSemi’s linearizer IP is open to any FPGA and ASIC as long as the FPGA and ASIC processing resources and interfaces are defined in advance.
NanoSemi’s adaptation engine can be implemented either in logic or ARM processor, depending on the system requirement and FPGA resource utilization.
What is a sampling rate of DAC in transmit path and ADC in observation receive path for NanoSemi’s DPD?
Sampling rate is set to at least 2.5x the maximum instantaneous bandwidth (iBW) targeted for the radio. If the largest bandwidth is 100MHz, the compensation bandwidth is 250MHz. If the digital filter inside the transceiver limits an operating bandwidth of DAC and ADC to 80%, the sampling rate of DAC is not equal to the compensation bandwidth. For instance, the compensation bandwidth is 245MHz if the sampling rate is 307MSPS w/ 80% usable bandwidth.
- Baseband signal, quality control and carrier configurations (component carrier width and carrier number) are provided to the input of NanoSemi’s CFR block.
- The gating signal transition should be >6us before and after the data transition
- Measure ACLR under different time slots
5 Watts GaN PA
7.1dB CF 0.01%, LTE20M_1C_20M with Linearization
5 Watts GaN PA
8.0dB CF 0.01%, LTE20M_3C_60M with Linearization
ACLR of transceiver used -65dBc for 20MHz LTE, depending on the type of CMOS technologies or discrete components.
The baseline performance of integrated transceiver + low-power driver is better than -49dBc for 100MHz, 5 LTE 20MHz carriers. For single 20MHz LTE after driver, the ACLR is < -52dBc.
ACLR < -52dBc, LTE20M_1C_20M, CMOS TRx + Driver
ACLR < -49dBc LTE20M_5C_100M CMOS TRx + Driver